1. Field of the Invention
This invention relates to a vertical double diffused MOSFET and method for manufacturing same, and more particularly to a vertical double diffused MOSFET manufactured through a self-aligned process which is applicable for switching power sources, AC adapters, battery chargers, motor control circuits, inverter illumination, DC/DC converters or the like, and a method for manufacturing such a device.
2. Description of the Prior Art
There is shown in FIG. 3 a conventional vertical double diffused MOSFET of the kind as above. The MOSFET 1 includes a semiconductor substrate 2 having a main body 2a and an epitaxial layer 2b. The semiconductor substrate 2 has a main diffusion region 3a formed in a surface thereof. The semiconductor substrate 2 has, on the surface, a gate electrode 5 having at least one window 5a formed through an oxide film 4. The semiconductor substrate 2 is formed, at its bottom surface, with a drain electrode 6. Also, in the surface of the semiconductor substrate 2, a channel diffusion region 3b and source diffusion region 3c is formed in relation to the gate electrode 5 at a peripheral edge of the window 5a. On the gate electrode 5 an insulation layer 7 is formed of oxide silicon containing phosphorus (PSG). Over the insulation layer 7, a metal interconnect layer (source electrode) 8 is formed connecting to a source diffusion region 3c.
In manufacturing a vertical double diffused MOSFET 1, an n-type epitaxial layer 2b and oxide film 9a is formed on an n-type semiconductor substrate (main body) 2a, as shown in FIG. 4A. The oxide film 9a at one part is removed by etching to form a window 9b. Through this window 9b boron (B) ions are implanted to the surface of the semiconductor substrate 2. After etch-removing oxide film 9a, the boron (B) ions are thermally diffused to thereby provide a main diffusion region 3a. Simultaneous with this, a not-shown thermal oxide film is formed. As shown in FIG. 4B, this thermal oxide film is etched under a predetermined condition into an oxide film 4 having a thick walled portion 9c. Subsequently, as shown in FIG. 4C a gate electrode 5 is formed on the oxide film 4, and part of the gate electrode is etched to thereby provide a window 5a. Then, boron (B) ions are implanted through, as a mask, the gate electrode 5 into the surface of the semiconductor substrate 2. The implanted boron ions are thermally diffused to form a channel diffusion region 3b. Further, phosphorus (P) ions are implanted through, as a mask, the gate electrode 5 and thick walled portion 9c to the surface of the semiconductor substrate 2. The implanted phosphorus ions are then thermally diffused to provide a source diffusion 3c. Then an insulation layer 7 is formed over the oxide film 4 and gate electrode 5, as shown in FIG. 4E. Subsequently, as shown in FIG. 4F, the insulation layer 7 and oxide film 4 is partly etched away to form a contact hole 9d. Thereafter, a metal interconnect layer 8 is formed on the insulation layer 7 in a manner of connected to the source diffusion region 3c, as shown in FIG. 3. Further, a drain electrode 6 is formed at the underside of the semiconductor substrate 2.
In the prior art, however, the insulation layer 7 has used silicon oxide containing phosphorus (PSG). Therefore, it has been impossible to completely block contaminants, such as mobile ions, from intruding into the electrode 5 during the manufacturing process or in an operational environment after manufacture. Due to this, there has been a problem that the gate electrode 5 deteriorates in electric characteristic (threshold voltage, etc) due to aging.
On the other hand, the thick walled portion 9c was formed in a separate process (FIG. 4B) from the process of forming the main diffusion region 3a (FIG. 4A), making the manufacture process complicated. Moreover, there existed a fear that misalignment might occur in each of the processes. If a misalignment is caused during the process of forming the thick walled portion 9c, the source diffusion regions 3c on the left and right of the thick walled portion 9c are formed into different widths with respect to each other. Thus, there has been a fear of causing variation in electric current amount to be supplied to these source diffusion regions 3c from the metal interconnect layer 8.